--- title: "Arpit Arun Kumaar" handle: "arpitak" url: "https://arpitak.com" markdown_url: "https://arpitak.com/index.md" email: "arpitarunkumaar@gmail.com" description: "Arpit Arun Kumaar (arpitak) — Honours Computer Engineering student at the University of Waterloo working on Product (MCP, Plugins, Evals & Agentic UX) at Carta. Previously Applied AI & Venture at Axiom Partners VC, Silicon IP Design Engineer Intern at Low Power Futures, Software Engineer Intern at Intrepid Financial, Systems Engineer Intern at St Marys Cement, and AI/Robotics researcher at the University of Waterloo." --- # Arpit Arun Kumaar Hi! Welcome to my corner of the internet. I value thoughtful disagreements and am always curious to see things from other perspectives. I also lose track of time playing the guitar and sitting by the ocean. ## Currently, I am: - Studying computer engineering at [University of Waterloo](https://uwaterloo.ca/) (Bachelor of Applied Sciences (BASc), Honours Computer Engineering Co-op, expected March 2027) - Working on all things MCP, Plugins, Evals & Agentic UX at [Carta](https://carta.com/) ## Before that I have: - Built tools enabling agentic workflows + a bit of AI/semi investment research [@Axiom](https://axiompartners.vc/) - Silicon Design Engineering Intern [@Low Power Futures](https://www.venturelab.ca/portfolio/low-power-futures) - Created: FP4/FP6 sum-of-products unit, [native IBERT LLM inference unit on an FPGA](https://arpitak.com/writing/ibert-fpga-impl), [SNN on an FPGA to predict collisions](https://github.com/arpitarunkumaar/energy-aware-fpga-snn) ## Education - **University of Waterloo** — Bachelor of Applied Sciences (BASc), Honours Computer Engineering Co-op (Expected Graduation: March 2027) - **Awards:** Term Distinction, President's Scholarship ## Experience ### [Carta](https://carta.com/) — Product — MCP, Plugins, Evals & Agentic UX (Kitchener, ON · Sept 2026 – Present) - Built sentiment evaluator to grade user sessions from MCP/plugin telemetry, improving scoring alignment from 50% to 95%; surfaced unmet customer requests that directly shaped >6 new plugin features and informed targeted client re-engagement. - Designed and built an agent-native experience prototype guiding investors through automated reporting setup for bespoke firm needs via interactive in-chat controls with MCP Apps and live report previews (won internal hackathon). - Automated feedback filing to open PR loop: enabled agents to auto-file MCP bugs and feature requests on users' behalf and routed them via Airflow to an internal coding harness for triage and automated PR creation, addressing 100+ reports in 2 weeks. - Quantified client-base AI tool adoption by count and ARR using AWS Bedrock to analyze client calls and inform GTM and integration priorities. - Led sessions with VC firm clients demonstrating agentic workflows tailored to their AI familiarity, usage, and MCP/plugin adoption. - Benchmarking open models to guide internal model selection, with planned GPU fine-tuning and autoresearch experiments. ### [Axiom Partners VC](https://axiompartners.vc/) — Applied AI & Venture (San Francisco, CA · Feb 2026 – Apr 2026) - Led development of MCP aggregator server and skill workflows to expedite VC sourcing with agent-driven founder research and outreach flows, saving ~10 hours/month per partner. - Developed eval framework for MCP server to trace agent failure patterns; iteratively refined tool schemas, descriptions, and scoring rubrics, reducing tool call error rates by 82% and improving LLM response quality from 65% to 91%. - Built automated legal-ops workflow to pull context, fill, and validate investment paperwork, cutting $10k annually in direct costs. - Synthesized ML research and competitive analysis into investment memos for the Managing Partner, informing evaluation of Seed–Series C opportunities across AI infrastructure and semiconductors. ### [Low Power Futures, Inc](https://www.venturelab.ca/portfolio/low-power-futures) — Silicon IP Design Engineer Intern (Markham, ON · May 2025 – Aug 2025) - Extended EDA toolchain support after identifying missing Lattice and Intel integrations, accelerating prospect IP validation timelines. ### [Intrepid Financial](https://intrepidatg.com/) — Software Engineer Intern (San Francisco, CA · Jan 2024 – Jun 2024) - Designed A/B tests across dashboard UX after identifying pain points in flows and onboarding, driving >10% reduction in support ticket volume. - Engineered core creator analytics dashboards with TypeScript and TanStack, iterating weekly upon continuous customer feedback. ### [St Marys Cement](https://vcna.com/) — Systems Engineer Intern (St Marys, ON · Jan 2024 – May 2024) - Diagnosed alert fatigue as root cause for 90% of missed fault actions through operator shadowing and interviews; led HMI UX redesign and devised priority-based alert architecture, achieving an 80% decrease in missed alarm rates and 70% visual noise reduction. - Engineered deadband algorithm-based program to centralize instrument data for operations tracking and failure diagnosis across 3 sites. ## Research & Hardware / AI Projects - **Human-centric AI Research — Conrad School of Entrepreneurship & Business, University of Waterloo** (May 2026 – Present): Investigating how LLM use influences human judgment under pressure, measuring willingness to edit AI-drafted messages and general confidence in AI responses; analyzed pilot findings to refine experiments testing how interface nudges affect both outcomes. - **Research Assistant — [Vision & Image Processing (VIP) Lab, University of Waterloo](https://github.com/huggingface/lerobot)** (May 2025 – Aug 2025): Benchmarked performance of imitation learning vs. Vision-Language-Action (VLA) models on robotic pick-and-place tasks; fine-tuned SmolVLA policies for LeRobot SO-101, demonstrating stronger out-of-distribution generalization with up to 25% higher success rates on unseen object configurations. - **[I-BERT Based LLM Hardware Architecture](https://arpitak.com/writing/ibert-fpga-impl)** (SystemVerilog, Vivado, Xilinx PYNQ Z1/Z2 FPGA, AXI-Stream): End-to-end quantized Transformer (IBERT) language model implemented in SystemVerilog RTL with 4x4 systolic arrays, cyclic memory bank address generators, pipelined Exp/GELU/LayerNorm, and FSM division, generating tokens natively on an FPGA. - **[Energy-Aware Spiking Neural Network (SNN) on an FPGA](https://github.com/arpitarunkumaar/energy-aware-fpga-snn)** (SystemVerilog, FPGA, Spiking Neural Networks): Spiking Neural Network (SNN) implemented on an FPGA to predict collisions. - **FP4/FP6 Sum-of-Products Hardware Unit** (SystemVerilog, Digital Hardware Design, Low-Precision Arithmetic): Low-precision floating-point (FP4/FP6) hardware sum-of-products compute unit. ## Skills - **Technical:** Python, SQL, Swift, C, TypeScript, React, TanStack, SystemVerilog, Vivado, GCP, AWS Bedrock, Airflow, Supabase, Snowflake, Docker, Pandas, Linux, Agentic AI Patterns, Model Context Protocol (MCP), MCP Apps, Vision-Language-Action (VLA) Models / LeRobot - **Product & Ops:** LLM Eval Design & Error Analysis, Agentic UX, Product Analytics, Experiment Design, A/B Testing, Customer & Market Research, AI Infrastructure & Semiconductor Venture Research ## Contact Feel free to reach out at [arpitarunkumaar@gmail.com](mailto:arpitarunkumaar@gmail.com). ## Writing - [The Songs We Keep](https://arpitak.com/writing/songs-we-keep) (2025-12-20) — on music, neural nostalgia and EOY reflections - [An Intimacy Conundrum](https://arpitak.com/writing/intimacy-conundrum) (2025-11-02) — collection of thoughts and conversations from the past few months - [IBERT LLM Implementation in Hardware](https://arpitak.com/writing/ibert-fpga-impl) (2025-09-05) — Implementation of an LLM in hardware using SystemVerilog ## Social Links - [Twitter / X](https://x.com/arpitarunkumaar) - [GitHub](https://github.com/arpitarunkumaar) - [Substack](https://substack.com/@arpitarunkumaar/likes) - [LinkedIn](https://www.linkedin.com/in/arpitarunkumaar/) - [Spotify](https://open.spotify.com/user/zp6ykurq8u1yy6qitl03dg5uc)